Jetson PCIe Controller Customizer
Configure per-controller PCIe state, lane width, and link speed on custom Jetson Thor or Orin carriers.
The skill explicitly limits itself to kernel-DT overlay edits and forbids editing ODMDATA; it requires user confirmation, stops on contradictions, forbids autonomous git reset --hard, and cross-checks pinmaps, schematics, and the UPHY sidecar. These controls reduce overreach and destructive behavior. Points are deducted because BSP/hardware commits still create external effects, backup and executable rollback procedures are not fully specified, sensitive-input handling is not addressed, and repository license metadata is NOASSERTION.
The workflow has detailed prerequisites, failure branches, dtc/fdtoverlay preflight checks, and troubleshooting guidance, making the happy path plausible from static reading. Points are deducted because no committed test suite or CI coverage of key paths is shown, and the frontmatter version 0.0.1 conflicts with the sidecar example generator_version 0.1.0; static calibration caps this at 10.
Invocation triggers, supported platforms, RC/EP boundaries, prerequisites, and the non-fit UPHY lane-allocation boundary are clearly stated for Jetson Thor/Orin custom carriers. Points are deducted because the skill depends heavily on specific documents, workspace layout, and sibling skills, while Chinese-language interaction and mainland-China reachability are not explicitly addressed; semantic boundary precision still depends on agent judgment.
The package has useful progressive documentation through procedure and gotchas files, states limitations and output format, and identifies NVIDIA ownership and licensing material. Points are deducted for missing recommended Instructions and Examples sections, an invalid author-format finding, inconsistent license descriptions between frontmatter and the skill card/repository, and no clear changelog or maintenance update path.
The skill specifies a directly relevant kernel-DT overlay output and covers topology, pins, lanes, speed, compatibility, and ODMDATA consistency. The benchmark reports Codex correctness of 85% and effectiveness of 54%, indicating measurable value. Points are deducted because only two positive tasks were evaluated, no negative tasks were included, real BSP/DTB/schematic/downstream-skill inputs remain necessary, and static review cannot confirm a flash-ready artifact; therefore it stays at or below 7.
The sources provide a traceable procedure, concrete commands, sidecar schema, provenance-comment requirements, and a fixed revision context; the benchmark records limited evaluation results. Points are deducted because no independently reproducible committed tests, CI evidence, or corroborating third-party artifacts are supplied, and the benchmark lacks raw reproducibility details; static calibration therefore limits this to 5.
- Execution modifies and commits BSP/device-tree repositories; preserve a recoverable revision and obtain operator confirmation of target, scope, and rollback before real changes.
- The skill depends on the UPHY sidecar, DTB, schematics, pinmaps, the Adaptation Guide, and multiple sibling skills; missing or mismatched inputs can produce incorrect lane or status configuration.
- The evaluation covers only two positive tasks and no negative tasks, so it does not establish avoidance of false triggers, abnormal-input handling, or successful real-device flashing.
- Clarify the version and license statements and add Instructions, Examples, CI/tests, and a documented maintenance update path.
What does this skill do, and when should you use it?
This skill configures PCIe controllers on custom Jetson Thor and Orin carrier boards. It combines UPHY state, reference device trees, carrier schematics, and pinmaps to produce kernel device-tree overlay fragments. It verifies consistency with already-committed ODMDATA but does not edit ODMDATA. Its output is a kernel-DT overlay commit in the bsp_sources hardware repository.
Reads the active target profile, Adaptation Guide, Module Design Guide, SoC TRM, reference DTB, carrier pinmap, schematic, and UPHY-state sidecar; compares PCIe topology; asks which controllers to customize; verifies CLKREQ, RST, and optional WAKE signals with pin_verifier.py; derives and confirms per-controller plans; appends fragment@N blocks to the composite custom overlay .dts; runs dtc and fdtoverlay preflight checks; cross-checks ODMDATA against the overlay; commits the overlay change; and writes a run-state JSON sidecar.
- Use it when a Jetson Thor custom carrier needs specific PCIe controllers enabled or disabled.
- Use it when a PCIe slot or M.2 receptacle does not enumerate after flashing.
- Use it when a PCIe link trains at the wrong lane width or speed.
- Use it after UPHY lane reallocation changes which PCIe controllers are enabled and the kernel-DT side must be updated.
What are this skill's strengths and limitations?
- Configures per-controller enablement, lane count, link speed, and RC/EP mode.
- Checks agreement between the kernel overlay and ODMDATA and reports contradictions.
- Requires carrier schematic and pinmap evidence for custom-carrier work.
- Keeps production compilation and flash-conf registration with jetson-build-source.
- Depends on the jetson-init-source, jetson-derive-carrier, and jetson-customize-uphy workflow.
- Refuses custom-carrier runs without both the schematic and pinmux XLS.
- RC mode is hard-pinned by default; EP requires an explicit override.
- Does not edit ODMDATA, compile the production dtbo, or register the flash-conf overlay.
- The SKILL.md does not describe an independent test suite or a tested platform matrix.
How do you install this skill?
Install the skill from the NVIDIA/skills collection with: npx skills add nvidia/skills --skill jetson-customize-pcie --yes. You can first inspect available skills with npx skills add nvidia/skills --list. No other installation method is documented in the source.
How do you use this skill?
Prepare an active profile, a Linux_for_Tegra Git source tree, the derived carrier configuration, the UPHY-state JSON produced by jetson-customize-uphy, the required hardware documents, and dtc on PATH. Then ask the loaded agent to “configure PCIe” or “enable PCIe controller.” The skill must run after jetson-customize-uphy and emits only kernel-DT overlay fragments; ODMDATA remains owned by that upstream skill.